‐the von Neumann bottleneck ‐the parameter update problem ‐the problem with (guaranteed) memory bandwidth (illustrate with 128 voice sampling synth)
‐pipelining ‐superscalar architectures ‐reduced (but powerful) instruction sets ‐register based architecture ‐single cycle instructions
‐fine grain parallelism: datalog, vector, anticipatory (should these be mentioned at all?)
‐as an addressing optimization for FFT and other radix‐two butterfly computations (Walsh‐Hadamard?)
‐for ring buffering and interpolation
‐both in prefix forms and as embedded in all instructions (or CPU registers) ‐as size optimization/simplification over specialized branching instructions/speed optimization ‐when ‐branches can be avoided, and ‐pipelines stay full
‐pinning aka lockdown ‐locked instruction caches work as high level microcode
‐esp. audio buses like AES/EBU and I2C(?)
‐constant tables and lookup instructions
‐bus logic integration ‐bus mastering ASICs and logic gate building blocks ‐DMA and IRQ in both directions ‐integrated DMA/IRQ controllers ‐the problem of bus bandwidth